1. Field of the Invention
The present invention relates to a method of manufacturing a magnetic random access memory (MRAM). More particularly, the present invention relates to a method of forming a magnetic tunnel junction (MTJ) for an MRAM.
2. Description of the Related Art
As shown in FIG. 1, an MRAM generally includes a transistor T serving as a switch and an MTJ layer S on which data having a value of “0” or “1” are recorded. In a conventional method of manufacturing an MRAM, a gate stack 12 including a gate electrode is formed on a semiconductor substrate 10, and then a source region 14 and a drain region 16 are respectively formed at either side of the gate stack 12, thereby completing the transistor T having switch functions shown in FIG. 1. In FIG. 1, reference numeral 11 represents field oxide layers. An interlayer dielectric layer 18 is formed on the semiconductor substrate 10, on which the transistor T has already been formed, to completely cover the transistor T. During the formation of the interlayer dielectric layer 18, a data line 20 is formed over the gate stack 12 to be covered with the interlayer dielectric layer 18 and to be in parallel with the gate stack 12. A contact hole 22, through which the drain region 16 is exposed, is formed in the interlayer dielectric layer 18. The contact hole 22 is filled with a conductive plug 24 having the same height as the interlayer dielectric layer 18, and then a pad conductive layer 26 is formed to contact the top surface of the conductive plug 24 on the interlayer dielectric layer 18. The pad conductive layer 26 is formed over the data line 20. The MTJ layer S is formed on a predetermined area of a top surface of the pad conductive layer 26 that corresponds to the data line 20, and then a second interlayer dielectric layer 28 is formed to cover the MTJ layer S and the pad conductive layer 26. A via hole 30 is formed in the second interlayer dielectric layer 28 so that a top surface of the MTJ layer S is exposed through the via hole 30. A bitline 32 filling the via hole 30 is formed on the second interlayer dielectric layer 28 to be perpendicular to the gate electrode and the data line 20.
A method of forming the MTJ layer S included in the MRAM shown in FIG. 1 will now be described with reference to FIGS. 2 and 3.
As shown in FIG. 2, a lower magnetic layer S1, an insulation layer S2, and an upper magnetic layer S3 are sequentially formed on a predetermined region of the pad conductive layer 26, and then a mask pattern M is formed on the upper magnetic layer S3 to define a place where the MTJ layer S will be formed. Thereafter, as shown in FIG. 3, the upper magnetic layer S3, the insulation layer S2, and the lower magnetic layer S1 are sequentially etched using the mask pattern M as an etching mask, and then the mask pattern M is removed, thus completing the MTJ layer S.
Here, an ion milling method using argon (Ar) gas, a dry etching method using chlorine gas, or a reactive ion etching method may be used to sequentially etch the upper magnetic layer S3, the insulation layer S2, and the lower magnetic layer S1.
The MTJ layer S may be formed using a lift-off process. For example, the MTJ layer S may be formed as follows. First, a photoresist layer pattern is formed on the pad conductive layer 26 so that a region where the MTJ layer S will be formed is exposed, and then the material layers S1 through S3 constituting the MTJ layer S are sequentially deposited on the exposed region. Thereafter, the photoresist layer pattern is removed so that the material layers S1 through S3 formed at regions other than the place where the MTJ layer S will be formed are removed.
The method of manufacturing an MRAM, which has been described above, causes various problems depending on the way the MTJ layer S is formed.
First, in the case of forming the MTJ layer S using an ion milling method, the MTJ layer S can hardly have a delicate pattern, and by-products of an etching process for forming the MTJ layer S may be deposited at either side of the MTJ layer S. As a result of the deposition, an ear-shaped deposit of material 34 is formed at either side of the MTJ layer S, as shown in FIG. 3. The deposited material 34 short-circuits the material layers constituting the MTJ layer S, and accordingly, a tunneling magneto resistance (TMR) and a TMR ratio decrease.
Second, in the case of forming the MTJ layer S by using a reactive ion etching method, an undercut may be generated at either side of the MTJ layer S, and thus a tunnel barrier layer, i.e., the insulation layer S2 interposed between the upper and lower magnetic layers S3 and S1, may be damaged after an etching process due to the defective profile of either side of the MTJ layer S.
Third, in the case of forming the MTJ layer S by performing a dry etching method using chlorine gas as an etching gas, a discontinuous side step difference may be generated between the upper and lower magnetic layers S3 and S1 and the insulation layer S2 after the dry etching process. In particular, the insulation layer S2 may be corroded by the etching gas remaining even after the etching process, thus deteriorating the reproducibility of the dry etching process. Therefore, it is difficult to form an MTJ layer to be smaller than a micro size by using the dry etching method.
Fourth, in the case of forming the MTJ layer S by using a lift-off method, productivity decreases.